As Moore's Law continues to fuel the ability to build ever increasinglycomplex system-on-chips (SoCs), achieving performance goals is rising as acritical challenge to completing designs. In particular, the systeminterconnect must efficiently service a diverse set of data flows with widelyranging quality-of-service (QoS) requirements. However, the known solutions foroff-chip interconnects such as large-scale networks are not necessarilyapplicable to the on-chip environment. Latency and memory constraints foron-chip interconnects are quite different from larger-scale interconnects. Thispaper introduces a novel on-chip interconnect arbitration scheme. We show howthis scheme can be distributed across a chip for high-speed implementation. Wecompare the performance of the arbitration scheme with other known interconnectarbitration schemes. Existing schemes typically focus heavily on either lowlatency of service for some initiators, or alternatively on guaranteedbandwidth delivery for other initiators. Our scheme allows service latency onsome initiators to be traded off smoothly against jitter bounds on otherinitiators, while still delivering bandwidth guarantees. This scheme is asubset of the QoS controls that are available in the SonicsMX? (SMX) product.
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